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Formation PCI Express 2.0Informations pratiquesCentre de formation ac6-formation

 Formation PCI Express 2.0


 ac6-formation, COURBEVOIE
 Formation inter entreprise / intra entreprise


Objectif * Packet switching benefits compared to shared busses are highlighted - The course explains the various traffic types that PCI Express supports.
* The use of virtual channels to match Quality of Service requirements is explained.
* The course describes the discovery sequence required to initialize the switches.
* The course details the various stages of the physical layer : 8b10b coding, scrambling, elastic buffer, clock recovery and link training sequence.
* This course handles PCIe gen2, but highlights any difference between gen1 and gen2 specifications.
* It has been designed by M. Guillaume Peron, a worldwide expert in PCIe technology.
Contenu THE TRANSITION TO PACKET SWITCHING
* PCI bus limitations
* The hub link bus
* PCI-X
* Solutions to increase the performance : differential transmission, packet switching

INTRODUCTION TO PCI EXPRESS
* Overview
* Topology
* Layer protocol
* Quality of Service
* The physical layer

THE PHYSICAL LAYER - LOGICAL SUB-BLOCK
* 8-bit / 10-bit coding
* The ordered sets
* Byte dispatching rules for multi-lane links
* Scrambling
* Elastic buffer operation, clock compensation sequences
* De-skew
* Power management: EIOS and EIEIOS sequences
* Reset signalling
* Link Training and Status State Machine [LTSSM]
* Lane reversal, polarity inversion
* Detect state
* Polling state
* Configuration state
* Clarifying what happens when a Lane is failing
* Recovery state
* L0, L0s, L1 and L2 states
* Disabled, Loopback and Hot Reset states
* Behavior of a loopback slave
* Related registers

THE PHYSICAL LAYER - ELECTRICAL SUB-BLOCK
* Explaining why 2.5GTps is not a subset of 5.0 GTps
* Jitter budgeting and measurement
* Transmitter specification, phase jitter filtering
* Output swing
* Transmitter margining
* Measurement setup for characterizing transmitters
* De-emphasis
* Receiver specification
* Receiver tolerancing at 5.0 GTps
* Return loss
* Receiver compliance eye diagram
* Skew
* Differential receiver detect
* Low power modes, Beacon signal

POWER MANAGEMENT
* Link state power management
* PCI Power Management software interface
* Native PCI Express power management mechanisms
* Power budgeting capability

PACKET ROUTING
* PCI basics
* Operation of PCI-to-PCI transparent bridge
* Packet routing by the address
* Packet routing by the ID
* Packet routed implicitely

TLP ACKNOWLEDGEMENT
* Acknowledgement objectives
* Counters / timers present in the transmitter and the receiver
* Sequences
* Cut-through switches

QUALITY OF SERVICE
* Introduction, traffic differentiation
* VC arbitration
* Port arbitration, switch model

FLOW CONTROL
* Overview, transmit credit principle
* Related counters
* Credit update frequency

TRANSACTION ORDERING
* PCI Producer / Consumer model
* Relaxed ordering permitted by PCI-X
* PCI Express transaction ordering rules

PACKET FORMAT
* Benefits of a packet oriented protocol
* TLP format
* DLLP format

INTERRUPT MANAGEMENT
* Message Signaled Interrupts
* PCI Express Interrupt Management

ERROR MANAGEMENT
* General principles
* PCI-like error management
* PCI Express basic error management
* PCI Express basic advanced error management

THE CONFIGURATION SPACE
* Root Complex Register Block [RCRB]
* PCI Express enumeration
* PCI-compatible configuration registers
* Expansion ROMs
* New features of PCI Express 2.0 :
* PCI Express Enhanced Configuration Access Mechanism
* Device serial number capability
* Root Complex link declaration capability
* Root Complex internal link control capability
* ACS extended capability

DEBUGGING A PCI EXPRESS SYSTEM
* Compliance lists
* The Serial Data Analyser from Lecroy, test of the physical layer
* Protocol analyser / exercicer from Lecroy
* Trace analysis
Niveau requis * Experience of a high speed digital bus such as PCI / PCI-X is mandatory.
Coût 1950 euros
Durée de la formation 4 jours

 

Mise à jour le 01 Mars 2011 
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